1. Field of the Invention
The present invention relates to a shift register and an organic light emitting display having the same, and more particularly, to a shift register that is capable of preventing malfunction caused by skew and slop between clock signals used in the shift register.
2. Discussion of the Background
Generally, a shift register shifts bits of information at least one position to the right or left. Such a shift register may include cascaded flip-flops in which an output of the first flip-flop is sequentially connected to an input of the immediately following flip-flop. All flip-flops simultaneously receive the same clock signal and inverted clock signal so that data shift simultaneously occurs in a stage-by-stage manner.
Shift registers are widely used in various fields. In particular, in display devices such as liquid crystal displays (LCDs), organic light emitting displays, plasma display panels (PDPs), and so forth, the shift register is typically used in a scan driving unit, which sequentially supplies a scan signal, or in an emission control driving unit, which controls light emission.
FIG. 1 is a circuit diagram of a conventional shift register, and FIG. 2 is a timing diagram for signals of the shift register of FIG. 1. The shift register has a plurality of flip-flops that are connected to each other in series, and FIG. 1 shows the case where the shift register has two flip-flops as a basic unit. Additionally, the shift register of FIG. 1 has a four-stack structure in which four transistors are stacked between the positive power supply voltage VDD and the negative power supply voltage VSS.
Referring to FIG. 1 and FIG. 2, a conventional shift register may include a first flip-flop FF1, which includes transistors MN1, MN2, MN3, MN4, MN5, MP1, MP2, MP3, MP4, and MP5, and a second flip flop FF2, which includes transistors MN6, MN7, MN8, MN9, MN10, MP6, MP7, MP8, MP9, and MP10. The two flip-flops FF1 and FF2 are connected to each other in series, and an output signal of the first flip-flop FF1, which receives a start pulse SP as an input signal, becomes an input signal of the second flip-flop FF2. Accordingly, the first flip flop FF1 delivers the input start pulse SP to the second flip-flop FF2 per one or half period of a clock signal CLK in synchronization with the clock signal CLK and an inverted clock signal CLKB.
Each flip-flop FF1 and FF2 repeatedly performs sampling and holding of the input signal in response to states of the clock signal CLK and the inverted clock signal CLKB of FIG. 2. That is, the first flip-flop FF1 detects the state of the input start pulse SP at a sampling time T1 and maintains that state at a holding time T2 in response to the input of the start pulse SP. The second flip-flop FF2 operates opposite to the first flip-flop FF1 such that it delivers the start pulse SP by sequentially sampling the state held by the first flip-flop FF1 and delivering it to the next flip-flop.
In the timing diagram of FIG. 2, which shows normal operation of the clock signal CLK and the inverted clock signal CLKB, a first output signal SR1 transitions to a low level just after the transition of the clock signal CLK and the inverted clock signal CLKB. Accordingly, a sampling region and a holding region of each flip-flop are correctly discriminated to generate a normal output signal.
However, as described below, the conventional shift register of FIG. 1 may malfunction when skew occurs between the clock signal CLK and the inverted clock signal CLKB or when slop increases.
FIG. 3 is a timing diagram showing an error of an output signal SR2 due to skew between the clock and inverted clock signals input to the shift register.
Referring to FIG. 3, the timing diagram shows skew in the clock signal CLK prior to the inverted clock signal CLKB. That is, referring to the skew interval, the inverted clock signal CLKB maintains a low level even after the clock signal CLK and the first output signal SR1 transition to a low level.
Accordingly, transistors MN1 and MN3 of the first flip-flop FF1 and transistors MN6 and MN8 of the second flip-flop FF2 of FIG. 1 are turned off, and transistors MP2 and MP4 of the first flip-flop FF1 and transistors MP7 and MP9 of the second flip-flop FF2 are turned on. In this case, as FIG. 3 shows, the second output signal SR2 transitions to a low level instead of maintaining the high level. Hence, an abnormal output signal may be output when the magnitude of the skew between the clock signal CLK and the inverted clock signal CLKB increases to more than a predetermined value.
FIG. 4 is a timing diagram showing an output signal error due to slop between the clock and inverted clock signals input to the conventional shift register. Here, the time from the moment an input signal is sampled by any flip-flop to the moment when the input signal is output is defined as Ts. Additionally, it is assumed that skew between the clock signals does not occur, and the clock signal CLK and the inverted clock signal CLKB are converted as shown in FIG. 4.
FIG. 4 shows the time Ton in which the clock signal CLK transitions from a threshold voltage Vthn of an N-type transistor through a threshold voltage Vthp of a P-type transistor while the inverted clock signal CLKB transitions from the threshold voltage Vthp through the threshold voltage Vthn.
Transistors MP2, MP4, MN1, MN3, MP7, MP9, MN6, and MN8 of FIG. 1 are turned on during the time Ton in which the slop occurs. Accordingly, when the slop of the clock signal CLK and the inverted clock signal CLKB increases and Ton exceeds Ts, output signals SR1, SR2, and SR3 of respective flip-flops FF1, FF2, and FF3, which must sequentially perform sampling and holding operations, operate as shown in FIG. 4. That is, each flip-flop FF1, FF2, and FF3 becomes a buffer in which two inverters are connected to each other in series. Accordingly, malfunction occurs in that the output signal SR1 becomes the next output signal SR2.
External noise or electromagnetic inference (EMI) may cause skew or slop in the clock signal CLK and the inverted clock signal CLKB, thereby causing an abnormal signal to be output from the shift register. This abnormal signal causes malfunction in a display device to which it is applied.